// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/05/CPU.hdl

/**
 * The Hack CPU (Central Processing unit), consisting of an ALU,
 * two registers named A and D, and a program counter named PC.
 * The CPU is designed to fetch and execute instructions written in 
 * the Hack machine language. In particular, functions as follows:
 * Executes the inputted instruction according to the Hack machine 
 * language specification. The D and A in the language specification
 * refer to CPU-resident registers, while M refers to the external
 * memory location addressed by A, i.e. to Memory[A]. The inM input 
 * holds the value of this location. If the current instruction needs 
 * to write a value to M, the value is placed in outM, the address 
 * of the target location is placed in the addressM output, and the 
 * writeM control bit is asserted. (When writeM==0, any value may 
 * appear in outM). The outM and writeM outputs are combinational: 
 * they are affected instantaneously by the execution of the current 
 * instruction. The addressM and pc outputs are clocked: although they 
 * are affected by the execution of the current instruction, they commit 
 * to their new values only in the next time step. If reset==1 then the 
 * CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather 
 * than to the address resulting from executing the current instruction. 
 */

CHIP CPU {

    IN  inM[16],         // M value input  (M = contents of RAM[A])
        instruction[16], // Instruction for execution
        reset;           // Signals whether to re-start the current
                         // program (reset==1) or continue executing
                         // the current program (reset==0).

    OUT outM[16],        // M value output
        writeM,          // Write to M? 
        addressM[15],    // Address in data memory (of M)
        pc[15];          // address of next instruction

    PARTS:
        // Put your code here:
        
        //p68~70より:instruction[12..15]=111a or 0vvv, instruction[6..11]=c1~c6, instruction[3..5]=d1~d3, instruction[0..2]=j1~j3
        
        //outAluはALU出力。p69付近よりinstruction[15]が0のときA命令、1のときC命令。
        //C命令かつinstruction[5]=1のときload=1であるが、実際には(instruction[5]=1でないとAレジスタに書き込めないので)instruction[15]のみの判定でOK
        Mux16(a[0..15]=instruction[0..15], b[0..15]=outAlu, sel=instruction[15], out[0..15]=toA);
        
        //Aレジスタ。instruction[15]が0又は、p72の図4-4よりinstruction[5]が1のときAレジスタに書き込み
        Not(in=instruction[15], out=n15);
        Or(a=n15, b=instruction[5], out=loadA);
        Register(in[0..15]=toA, load=loadA, out[0..15]=outA, out[0..14]=addressM[0..14]);
        
        //入力はAレジスタと、inMから。出力はALUへ。p71の図4-3より、instruction[12]=aが0のときAレジスタを、1のときinMを使用
        Mux16(a[0..15]=outA, b[0..15]=inM[0..15], sel=instruction[12], out[0..15]=toAlu);
        
        //Decoder
        //結局HackのdecoderはPCのloadを1にするか0にするかの条件検討のみでよい
        //instruction[15]が0でないとき、p73の図4-5より、(instruction[2]=1かつng=1)または(instruction[1]=1かつzr=1)または(instruction[0]=1かつng=0かつzr=0)のときload=1
        And(a=instruction[2], b=ng, out=and2);
        And(a=instruction[1], b=zr, out=and1);
        Not(in=ng, out=nng);
        Not(in=zr, out=nzr);
        And(a=nng, b=nzr, out=andNngzr);
        And(a=instruction[0], b=andNngzr, out=and0);
        Or(a=and2, b=and1, out=or1);
        Or(a=and0, b=or1, out=or2);
        And(a=instruction[15], b=or2, out=loadPC);
        
        //リセット付き、プログラムカウンタ
        //reset=1のとき出力は全て0、reset=0でload=1のとき、in(=outA)が出力される。reset=0,load=0でinc=1のときpc+1が出力される。そうでなければそのまま出力
        PC(in[0..15]=outA, reset=reset, load=loadPC, inc=true, out[0..14]=pc[0..14]);
        
        //HACKの算術仕様はp71の図4-3とp36の図2-6を参照。c1~c6=instruction[6..11]を使う。yにはinstruction[12]=a=0のときAが、a=1のときinMが入る。xはDレジスタ。
        ALU(x[0..15]=outD, y[0..15]=toAlu, zx=instruction[11], nx=instruction[10], zy=instruction[9], ny=instruction[8], f=instruction[7], no=instruction[6], out[0..15]=outM[0..15], out[0..15]=outAlu, zr=zr, ng=ng);
        //Dレジスタ。instruction[15]が1かつ、p72の図4-4よりinstruction[4]が1のときDレジスタに書き込み
        And(a=instruction[15], b=instruction[4], out=loadD);
        Register(in[0..15]=outAlu, load=loadD, out[0..15]=outD);
        
        //p72の図4-4より
        And(a=instruction[15], b=instruction[3], out=writeM);
}